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L9954 L9954XP
Door actuator driver
Features

Three half bridges for 1.5A load (Ron=800m) One highside driver for 6A load (Ron=100m) Two highside drivers for 1.5A load (Ron=800m) Programmable softstart function to drive loads with higher inrush currents (i.e. current >6A, >1.5A) Very low current consumption in standby mode (IS < 6A typ; Tj 85 C) All outputs short circuit protected Current monitor output for highside OUT1, OUT4, OUT5 and OUT6 All outputs over temperature protected Open load diagnostic for all outputs Overload diagnostic for all outputs PWM control of all outputs Charge pump output for reverse polarity protection
PowerSO-36 PowerSSO-36

Applications
Door actuator driver with bridges for mirror axis control and highside driver for mirror defroster and two 10W-light bulbs.
Description
The L9954 and L9954XP are microcontroller driven, multifunctional door actuator drivers for automotive applications. Up to two DC motors and three grounded resistive loads can be driven with three half bridges and three highside drivers. The integrated standard serial peripheral interface (SPI) controls all operation modes (forward, reverse, brake and high impedance). All diagnostic information is available via the SPI.
Table 1.
Device summary
Order codes Package Tube PowerSO-36 PowerSSO-36 L9954 L9954XP Tape and reel L9954TR L9954XPTR
May 2010
Doc ID 14279 Rev 3
1/37
www.st.com 1
Contents
L9954 / L9954XP
Contents
1 2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 2.4 2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . 20 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 20 Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Over load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Programmable softstart function to drive loads with higher inrush current 22
4
Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 4.2 4.3 4.4 4.5 4.6 4.7 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Serial clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Input data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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L9954 / L9954XP
Contents
4.8
SPI - Input data and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5 6
Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1 6.2 6.3 6.4 6.5 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PowerSO-36TM package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PowerSSO-36TM package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PowerSO-36TM packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PowerSSO-36TM packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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List of tables
L9954 / L9954XP
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 OUT1 - OUT6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SPI - input data and status registers 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SPI - input data and status registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PowerSO-36TM mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PowerSSO-36TM mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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L9954 / L9954XP
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI - DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI - driver turn on / off timing, minimum CSN HI time. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Example of programmable softstart function for inductive loads . . . . . . . . . . . . . . . . . . . . 22 Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PowerSO-36TM package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PowerSSO-36TM package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PowerSO-36TM tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PowerSO-36TM tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PowerSSO-36TM tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PowerSSO-36TM tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Block diagram and pin description
L9954 / L9954XP
1
Block diagram and pin description
Figure 1. Block diagram
VBAT Reverse Polarity Protection
* Note: Value of capacitor has to be choosen carefully to limit the VS voltage below absolute
100k
*
100F
10k
maximum ratings in case of an unexpected freewheeling condition (e.g. TSD, POR)
VS
VCC
Charge Pump
Driver Interface & Diagnostic
VCC
OUT1 OUT2 OUT3
Mirror Common M M Mirror Vertical Mirror Horizontal
SPI Interface
** 1k ** 1k ** 1k ** 1k **1k
DI DO CLK CSN
Lock / Folder
OUT4 OUT5
PWM1
Programmable Bulb (10W) or LED Mode Defroster
C
OUT6
**1k
PWM2 / CM
MUX
4
GND
** Note: Resistors between C and L9954LXP are recommended to limit currents for negative voltage transients at VBAT (e.g. ISO type 1 pulse)
Table 2.
Pin
Pin definitions and functions
Symbol Function Ground : Reference potential Important: for the capability of driving the full current at the outputs all pins of GND must be externally connected. Highside-driver-output 6 The output is built by a highside switch and is intended for resistive loads, hence the internal reverse diode from GND to the output is missing. For ESD reason a diode to GND is present but the energy which can be dissipated is limited. The highside driver is a power DMOS transistor with an internal parasitic reverse diode from the output to VS (bulk-drain-diode). The output is over-current and open load protected. Important: for the capability of driving the full current at the outputs both pins of OUT6 must be externally connected.
1, 18, 19, 36
GND
2, 35
OUT6
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Doc ID 14279 Rev 3
L9954 / L9954XP Table 2.
Pin
Block diagram and pin description Pin definitions and functions (continued)
Symbol Function Half-bridge-output 1,2,3 The output is built by a highside and a lowside switch, which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: highside driver from output to VS, lowside driver from GND to output). This output is over-current and open load protected. Power supply voltage (external reverse protection required) For this input a ceramic capacitor as close as possible to GND is recommended. Important: for the capability of driving the full current at the outputs all pins of VS must be externally connected. Serial data input The input requires CMOS logic levels and receives serial data from the microcontroller. The data is an 24bit control word and the least significant bit (LSB, bit 0) is transferred first.
3 4 5
OUT1 OUT2 OUT3
6, 7, 14, 25, 28, 32
VS
8
DI
9
Current monitor output/PWM2 input Depending on the selected multiplexer bits of Input Data Register this CM/PWM2 output sources an image of the instant current through the corresponding highside driver with a ratio of 1/10.000. This pin is bidirectional. The microcontroller can overdrive the current monitor signal to provide a second PWM input for the output OUT5. Chip select not input / testmode This input is low active and requires CMOS logic levels. The serial data transfer between L9954 and micro controller is enabled by pulling the input CSN to low level. Serial data output The diagnosis data is available via the SPI and this tristate-output. The output will remain in tristate, if the chip is not selected by the input CSN (CSN = high) Logic supply voltage For this input a ceramic capacitor as close as possible to GND is recommended. Serial clock input This input controls the internal shift register of the SPI and requires CMOS logic levels. Charge pump output This output is provided to drive the gate of an external n-channel power MOS used for reverse polarity protection. PWM1 input This input signal can be used to control the drivers OUT1-OUT4 and OUT6 by an external PWM signal.
10
CSN
11
DO
12
VCC
13
CLK
26
CP
27
PWM1
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Block diagram and pin description Table 2.
Pin
L9954 / L9954XP
Pin definitions and functions (continued)
Symbol Function Highside-driver-output 4 and 5 Each output is built by a highside switch and is intended for resistive loads, hence the internal reverse diode from GND to the output is missing. For ESD reason a diode to GND is present but the energy which can be dissipated is limited. Each highside driver is a power DMOS transistor with an internal parasitic reverse diode from each output to VS (bulk-drain-diode). Each output is over-current and open load protected. Not connected pins.
31 33
OUT4, OUT5
15, 16, 17, 20, 21, 22, 23, 24, 29, 30, 34
NC
Figure 2.
Configuration diagram (top view)
GND 1 OUT6 2 OUT1 3 OUT2 4 OUT3 5 Vs 6 Vs 7 DI 8 CM / PWM2 9 CSN 10 DO 11 Vcc 12 CLK 13 Vs 14 NC 15 NC 16 NC 17 GND 18
36 GND 35 OUT6 34 NC 33 OUT5 32 Vs 31 OUT4
PowerSO-36 PowerSSO-36
30 NC 29 NC 28 Vs 27 PWM1 26 CP 25 Vs 24 NC 23 NC 22 NC 21 NC 20 NC 19 GND
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Doc ID 14279 Rev 3
L9954 / L9954XP
Electrical specifications
2
2.1
Electrical specifications
Absolute maximum ratings
Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
DC supply voltage VS VCC VDI, VDO, VCLK, VCSN, Vpwm1 VCM VCP IOUT1,2,3,4,5 IOUT6 Single pulse tmax < 400ms Stabilized supply voltage, logic supply Digital input / output voltage Current monitor output Charge pump output Output current Output current
-0.3 to28 40 -0.3 to 5.5 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -25 to VS + 11 5 10
V V V V V V A A
2.2
ESD protection
Table 4. ESD protection
Parameter Value 2 (1) 8
(2)
Unit
All pins Output pins: OUT1 - OUT6
1. HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A. 2. HBM with all unzapped pins grounded.
kV kV
2.3
Thermal data
Table 5.
Symbol
Operating junction temperature
Parameter Value Unit
Tj
Operating junction temperature
-40 to 150
C
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Electrical specifications Table 6.
Symbol
L9954 / L9954XP
Temperature warning and thermal shutdown
Parameter Min. Typ. Max. Unit
TjTW ON TjSD ON TjSD OFF
Temperature warning threshold junction temperature Thermal shutdown threshold junction temperature Thermal shutdown threshold junction temperature
Tj Tj increasing Tj decreasing
130
150 170
C C C
150 5
TjSD HYS Thermal shutdown hysteresis
K
2.4
Electrical characteristics
VS = 8 to 16V, VCC = 4.5 to 5.3V, Tj = - 40 to 150C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. Table 7.
Symbol
Supply
Parameter Test condition Min. Typ. Max Unit
VS
Operating supply voltage range VS DC supply current VS = 16V, VCC = 5.3V active mode OUT1 - OUT6 floating VS = 16V, VCC = 0V standby mode OUT1 - OUT6 floating Ttest = -40C, 25C Ttest = 85C (1) VCC DC supply current VS = 16V, VCC = 5.3V CSN = VCC , active mode VS = 16V, VCC = 5.3V CSN = VCC standby mode OUT1 - OUT6 floating VS = 16V, VCC = 5.3V CSN = VCC standby mode OUT1 - OUT6 floating Ttest = 130C
7
28
V
7
20
mA
IS VS quiescent supply current
4
12
A
6 1
25 3
A mA
ICC
VCC quiescent supply current
25
50
A
IS + ICC
Sum quiescent supply current
50
100
A
1. Guaranteed by design.
10/37
Doc ID 14279 Rev 3
L9954 / L9954XP Table 8.
Symbol
Electrical specifications Overvoltage and undervoltage detection
Parameter Test condition Min. Typ. Max Unit
VSUV ON VS UV-threshold voltage VSUV OFF VS UV-threshold voltage VSUV hyst VS UV-hysteresis VSOV OFF VS OV-threshold voltage VSOV ON VS OV-threshold voltage VSOV hyst VS OV-hysteresis VPOR OFF Power-On-reset threshold VPOR ON Power-On-reset threshold VPOR hyst Power-On-reset hysteresis
VS increasing VS decreasing VSUV ON - VSUV OFF VS increasing VS decreasing VSOV OFF - VSOV ON VCC increasing VCC decreasing VPOR OFF - VPOR ON
5.7 5.5 0.5 18 17.5 1
7.2 6.9
V V V
24.5 23.5
V V V
4.4 3.1 0.3
V V V
Table 9.
Symbol
Current monitor output
Parameter Test condition Min. Typ. Max. Unit
VCM ICM,r
Functional voltage range Current monitor output ratio: ICM / IOUT1,4,5,6
VCC = 5V 0V VCM 4V, VCC=5V 0 V VCM 3.8V, VCC = 5V, IOut,min=500mA, IOut max = 6A (FS = full scale= 600A)
0 1----------------10.000
4
V -
ICM acc
Current monitor accuracy
4% + 1%FS
8% + 2%FS
-
Table 10.
Symbol
Charge pump output
Parameter Test condition Min. Typ. Max. Unit
VS = 8V, ICP = -60A VCP Charge pump output voltage Charge pump output current VS = 10V, ICP = -80A VS 12V, ICP = -100A ICP VCP = VS+10V, VS =13.5V
VS+6 VS+8 VS+10 95 150
VS+13 VS+13 VS+13 300
V V V A
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Electrical specifications Table 11.
Symbol
L9954 / L9954XP
OUT1 - OUT6
Parameter Test condition Min. Typ. Max. Unit
rON OUT1, rON OUT2 On-resistance to supply or GND rON OUT3
VS = 13.5 V, Tj = 25 C, IOUT1,2,3 = 0.8A VS = 13.5 V, Tj = 125 C, IOUT1,2,3 = 0.8 A VS = 13.5 V, Tj = 25 C, IOUT4,5 = -0.8 A VS = 13.5 V, Tj = 125 C, IOUT4,5 = -0.8 A VS = 13.5 V, Tj = 25 C, IOUT6 = - 3 A VS = 13.5 V, Tj = 125 C, IOUT6 = -3 A Source, VS=13.5 V -3.0
800 1250 500 700 100 150
1100 1700 700 950 150 200
m m m m m m
rON OUT4, On-resistance to supply rON OUT5
rON OUT6 On-resistance to supply
IOUT1 IOUT2 IOUT3 IOUT1 IOUT2 IOUT3 IOUT4 IOUT5 IOUT6
Output current limitation to GND
-1.5
A
Output current limitation to supply Output current limitation to GND Output current limitation to GND Output delay time, highside driver On Output delay time, highside driver Off Output delay time, lowside driver On Output delay time, lowside driver Off Cross current protection time, source to sink Cross current protection time, sink to source
Sink, VS=13.5 V
1.5
3.0
A
Source, VS=13.5 V Source, VS=13.5 V VS=13.5 V, corresponding lowside driver is not active VS=13.5 V VS=13.5 V, corresponding highside driver is not active VS=13.5 V
tCC ONLS_OFFHS - td OFF H(1) tCC ONHS_OFFLS - td OFF L(1)
-3.0 -10.5
-1.5 -6
A A
td ON H
20
40
80
s
td OFF H
50
150
300
s
td ON L
15
30
70
s
td OFF L td HL td LH
80
150 200 200
300 400 400 -5 0
s s s A A
IQLH
VOUT1-6= 0V, standby Switched-off output current highside drivers of mode OUT1-6 VOUT1-6= 0V, active mode
0 -40
-2 -15
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L9954 / L9954XP Table 11.
Symbol
Electrical specifications OUT1 - OUT6 (continued)
Parameter Test condition Min. Typ. Max. Unit
IQLL
Switched-off output current lowside drivers of OUT1-3 Open load detection current of OUT1, OUT2 and OUT3 Open load detection current of OUT4 and OUT5 Open load detection current of OUT6 Minimum duration of open load condition to set the status bit Minimum duration of over-current condition to switch off the driver Recovery frequency for OC recovery duty cycle bit=0 Recovery frequency for OC recovery duty cycle bit=1
VOUT1-3= VS, standby mode VOUT1-3= VS, active mode Source and sink
0 -40 15
80 -15 40
120 0 60
A A mA
IOLD123
IOLD45
Source and sink
15
40
60
mA
IOLD6
Source
30
150
300
mA
td OL
500
3000
s
tISC
10
100
s
frec0
1
4
kHz
frec1
2 VS =13.5 V Rload = 16.8 VS =13.5 V Rload = 4.5
6
kHz
dVOUT123/dt Slew rate of OUT123 and dVOUT45/dt OUT 45 dVOUT6/dt Slew rate of OUT6
0.08 0.08
0.2 0.2
0.4 0.4
V/s V/s
1. tCC ON is the switch on delay time td ON if complement in half bridge has to switch Off.
2.5
SPI - electrical characteristics
(VS = 8 to 16V, VCC = 4.5 to 5.3V, Tj = - 40 to 150C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin). Table 12.
Symbol
Delay time from standby to active mode
Parameter Test condition Min. Typ. Max. Unit
tset
Delay time
Switching from standby to active mode. Time until output drivers are enabled after CSN going to high.
160
300
s
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Electrical specifications Table 13.
Symbol
L9954 / L9954XP
Inputs: CSN, CLK, PWM1/2 and DI
Parameter Test condition Min. Typ. Max. Unit
VinL VinH VinHyst ICSN in ICLK in IDI in IPWM1 in Cin(1)
Input low level Input high level Input hysteresis Pull up current at input CSN Pull down current at input CLK Pull down current at input DI Pull down current at input PWM1 Input capacitance at input CSN, CLK, DI and PWM1/2
VCC = 5V VCC = 5V VCC = 5V VCSN = 3.5V VCC = 5V VCLK = 1.5V VDI = 1.5V VPWM = 1.5V 0 V < VCC < 5.3V
1.5
2.0 3.0 3.5
V V V
0.5 -40 10 10 10 -20 25 25 25 10 -5 50 50 50 15
A A A A pF
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 14.
Symbol
DI timing (1)
Parameter Test condition Min. Typ. Max. Unit
tCLK tCLKH tCLKL tset CSN tset CLK tset DI thold DI tr in tf in
Clock period Clock high time Clock low time CSN setup time, CSN low before rising edge of CLK CLK setup time, CLK high before rising edge of CSN DI setup time DI hold time Rise time of input signal DI, CLK, CSN Fall time of input signal DI, CLK, CSN
VCC = 5V VCC = 5V VCC = 5V VCC = 5V VCC = 5V VCC = 5V VCC = 5V VCC = 5V VCC = 5V
1000 400 400 400 400 200 200 100 100
ns ns ns ns ns ns ns ns ns
1. DI timing parameters tested in production by a passed / failed test: Tj= -40C / +25C: Tj= +125C SPI communication @ 2MHz. SPI communication @ 1.25 MHz.
Table 15.
Symbol
DO
Parameter Test condition Min. Typ. Max. Unit
VDOL VDOH
Output low level Output high level
VCC = 5 V, ID = -2mA VCC = 5 V, ID = 2 mA
0.2 VCC -0.4 VCC-0.2
0.4
V V
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L9954 / L9954XP Table 15.
Symbol
Electrical specifications DO (continued)
Parameter Test condition Min. Typ. Max. Unit
IDOLK CDO (1)
Tristate leakage current Tristate input capacitance
VCSN = VCC, 0V < VDO < VCC VCSN = VCC, 0V < VCC < 5.3V
-10 10
10 15
A pF
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 16.
Symbol
DO timing
Parameter Test condition Min. Typ. Max. Unit
tr DO tf DO ten DO tri L tdis DO L tri ten DO tri H tdis DO H tri td DO
DO rise time DO fall time DO enable time from tristate to low level DO disable time from low level to tristate
CL = 100 pF, Iload = -1mA CL = 100 pF, Iload = 1mA CL = 100 pF, Iload = 1mA pull-up load to VCC CL = 100 pF, Iload = 4 mA pull-up load to VCC
80 50 100 380 100 380 50
140 100 250 450 250 450 250
ns ns ns ns ns ns ns
DO enable time CL =100 pF, Iload = -1mA from tristate to high level pull-down load to GND DO disable time CL = 100 pF, Iload = -4mA from high level to tristate pull-down load to GND DO delay time VDO < 0.3 VCC, VDO > 0.7VCC, CL = 100pF
Table 17.
Symbol
CSN timing
Parameter Test condition Min. Typ. Max. Unit
tCSN_HI,stb
CSN HI time, switching from standby mode
Transfer of SPI-command to Input Register Transfer of SPI-command to input register
20 4
s s
tCSN_HI,min CSN HI time, active mode
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Electrical specifications Figure 3. SPI - transfer timing diagram
CSN high to low: DO enabled
L9954 / L9954XP
CSN
time
CLK
0
1
2
3
4
5
6
7
X
X
18 19
20 21 22 23
0
1
DI: data will be accepted on the rising edge of CLK signal
time
0 1
DI
0
1
2
3
4
5
6
7
X
X
18 19
20 21 22 23
DO: data will change on the falling edge of CLK signal
time
0 1
DO
0
1
2
3
4
5
6
7
X
X
18 19
20 21 22
23
fault bit
CSN low to high: actual data is transfered to output power switches old data new data
time
Input Data Register
time
Figure 4.
SPI - input timing
0.8 VCC 0.2 VCC t
set CSN
CSN t
CLKH
t
se t CLK
CLK t
set DI
0.8 VCC 0.2 VCC t
hold DI
t
CLKL
0.8 VCC DI Valid Valid 0.2 VCC
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L9954 / L9954XP Figure 5. SPI - DO valid data delay time and valid time
t f in t r in
Electrical specifications
CLK t r DO DO (low to high) t d DO DO (high to low) t f DO
0.8 VCC 0.5 VCC 0.2 VCC
0.8 VCC 0.2 VCC
0.8 VCC 0.2 VCC
Figure 6.
SPI - DO enable and disable time
tf in tr in
CSN
0.8 VCC 50% 0.2 VCC
DO pull-up load to VCC CL = 100 pF
50%
ten DO tri L t dis DO L tri
DO pull-down load to GND CL = 100 pF ten DO tri H t dis DO H tri
50%
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Electrical specifications Figure 7. SPI - driver turn on / off timing, minimum CSN HI time
CSN low to high: data from shift register is transferred to output power switches
L9954 / L9954XP
t r in
tCSN_HI,min
t f in
CSN
80% 50% 20% tdOFF
output current of a driver
ON state
OFF state
80% 50% 20%
t OFF tdON t ON output current of a driver 80% 50% 20%
OFF state
ON state
Figure 8.
SPI - timing of status bit 0 (fault condition)
CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO
CSN time CLK time DI time
DI: data is not accepted
DO
0 time
DO: status information of data bit 0 (fault condition) will stay as long as CSN is low
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L9954 / L9954XP
Application information
3
3.1
Application information
Dual power supply: VS and VCC
The power supply voltage VS supplies the half bridges and the highside drivers. An internal charge-pump is used to drive the highside switches. The logic supply voltage VCC (stabilized 5 V) is used for the logic part and the SPI of the device. Due to the independent logic supply voltage the control and status information will not be lost, if there are temporary spikes or glitches on the power supply voltage. In case of poweron (VCC increases from undervoltage to VPOR OFF = 4.2 V) the circuit is initialized by an internally generated power-on-reset (POR). If the voltage VCC decreases under the minimum threshold (VPOR ON = 3.4 V), the outputs are switched to tristate (high impedance) and the status registers are cleared.
3.2
Standby mode
The standby mode of the L9954 is activated by clearing the bit 23 of the Input Data Register 0. All latched data will be cleared and the inputs and outputs are switched to high impedance. In the standby mode the current at VS (VCC) is less than 6 A (50A) for CSN = high (DO in tristate). By switching the VCC voltage a very low quiescent current can be achieved. If bit 23 is set, the device will be switched to active mode.
3.3
Inductive loads
Each half bridge is built by an internally connected highside and a lowside power DMOS transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1 to OUT3 without external free-wheeling diodes. The highside drivers OUT4 to OUT6 are intended to drive resistive loads. Hence only a limited energy (E<1mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For inductive loads (L>100H) an external free-wheeling diode connected to GND and the corresponding output is needed.
3.4
Diagnostic functions
All diagnostic functions (over/open load, power supply over-/undervoltage, temperature warning and thermal shutdown) are internally filtered and the condition has to be valid for at least 32 s (open load: 1ms, respectively) before the corresponding status bit in the status registers will be set. The filters are used to improve the noise immunity of the device. Open load and temperature warning function are intended for information purpose and will not change the state of the output drivers. On contrary, the overload condition will disable the corresponding driver (over-current) and overtemperature will switch off all drivers (thermal shutdown). Without setting the over-current recovery bits in the Input Data register, the microcontroller has to clear the over-current status bits to reactivate the corresponding drivers.
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Application information
L9954 / L9954XP
3.5
Overvoltage and undervoltage detection
If the power supply voltage VS rises above the overvoltage threshold VSOV OFF (typical 21 V), the outputs OUT1 to OUT6 are switched to high impedance state to protect the load. When the voltage VS drops below the undervoltage threshold VSUV OFF (UV-switch-OFF voltage), the output stages are switched to the high impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). If the supply voltage VS recovers (register 0: bit 20=0) to normal operating voltage the outputs stages return to the programmed state after at least 32 s. If the undervoltage/overvoltage recovery disable bit is set, the automatic turn-on of the drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the drivers. It is strongly recommended to set bit 20 to avoid a possible high current oscillation in case of a shorted output to GND and low battery voltage.
3.6
Charge pump
The charge pump runs under all conditions in normal mode. In standby the charge pump is out of action.
3.7
Temperature warning and thermal shutdown
If junction temperature rises above Tj TW a temperature warning flag is set after at least 32 s and is detectable via the SPI. If junction temperature increases above the second threshold Tj SD, the thermal shutdown bit will be set and power DMOS transistors of all output stages are switched off to protect the device after at least 32 s. Temperature warning flag and thermal shutdown bit are latched and must be cleared by the microcontroller. The related bit is only cleared if the temperature decreases below the trigger temperature. If the thermal shutdown bit has been cleared the output stages are reactivated.
3.8
Open-load detection
The open load detection monitors the load current in each activated output stage. If the load current is below the open load detection threshold for at least 1 ms (tdOL) the corresponding open load bit is set in the status register. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3ms) can be used to test the open load status without changing the mechanical/electrical state of the loads.
3.9
Over load detection
In case of an over-current condition a flag is set in the status register in the same way as open load detection. If the over-current signal is valid for at least tISC = 32 s, the overcurrent flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. If the over-current recovery bit of the output is zero the microcontroller has to clear the status bits to reactivate the corresponding driver.
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L9954 / L9954XP
Application information
3.10
Current monitor
The current monitor output sources a current image at the current monitor output which has a fixed ratio (1/10000) of the instantaneous current of the selected highside driver. Signal at output CM is blanked after switching on of driver until correct settlement of circuitry (at least for 32 s). The bits 18 and 19 of the Input Data Register 0 control which of the outputs OUT1, OUT4, OUT5 and OUT6 will be multiplexed to the current monitor output. The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open- or overload condition. For example this can be used to detect the motor state (starting, free-running, stalled). Moreover, it is possible to regulate the power of the defroster more precise by measuring the load current. The current monitor output is bidirectional (c.f. PWM inputs).
3.11
PWM inputs
Each driver has a corresponding PWM enable bit which can be programmed by the SPI interface. If the PWM enable bit in Input Data Register 1 is set , the output is controlled by the logically AND-combination of the PWM signal and the output control bit in Input Data Register 0. The outputs OUT1-OUT4 and OUT6 are controlled by the PWM1 input and the output OUT5 is controlled by the bidirectional input CM/PMW2. For example, the two PWM inputs can be used to dim two lamps independently by external PWM signals.
3.12
Cross-current protection
The three half-bridges of the device are cross-current protected by an internal delay time. If one driver (LS or HS) is turned-off the activation of the other driver of the same half bridge will be automatically delayed by the cross-current protection time. After the cross-current protection time is expired the slew-rate limited switch-off phase of the driver will be changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to this behavior it is always guaranteed that the previously activated driver is totally turned-off before the opposite driver will start to conduct.
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Application information
L9954 / L9954XP
3.13
Programmable softstart function to drive loads with higher inrush current
Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps, start current of motors and cold resistance of heaters) can be driven by using the programmable softstart function (i.e. overcurrent recovery mode). Each driver has a corresponding over-current recovery bit. If this bit is set, the device will automatically switchon the outputs again after a programmable recovery time. The duty cycle in over-current condition can be programmed by the SPI interface to be about 15% ...25%. The PWM modulated current will provide sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition. The PWM frequency settles at 1.5 kHz or 3 kHz. The device itself cannot distinguish between a real overload and a non linear load like a light bulb. A real overload condition can only be qualified by time. As an example the microcontroller can switch on light bulbs by setting the over-current recovery bit for the first 50ms. After clearing the recovery bit the output will be automatically disabled if the overload condition still exits. Figure 9. Example of programmable softstart function for inductive loads
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L9954 / L9954XP
Functional description of the SPI
4
4.1
Functional description of the SPI
Serial Peripheral Interface (SPI)
This device uses a standard SPI to communicate with a microcontroller. The SPI can be driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0. For this mode, input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK. This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible output pins and one input pin will be needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect the status bit 0 (fault condition) of the device which is a logical-or of all bits in the status registers 0 and 1. The microcontroller can poll the status of the device without the need of a full SPIcommunication cycle.
Note:
In contrast to the SPI-standard the least significant bit (LSB) will be transferred first (see Figure 3).
4.2
Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) will be in high impedance state. A low signal will activate the output driver and a serial communication can be started. The state when CSN is going low until the rising edge of CSN will be called a communication frame. If the CSN-input pin is driven above 7.5V, the L9954 will go into a test mode. In the test mode the DO will go from tri-state to active mode.
4.3
Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register. At the rising edge of the CSN signal the contents of the shift register will be transferred to Data Input Register. The writing to the selected Data Input Register is only enabled if exactly 24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame.
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended.
4.4
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the status bit 0 (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer the
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Functional description of the SPI
L9954 / L9954XP
content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out.
4.5
Serial clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal.
4.6
Input data register
The device has two input registers. The first bit (bit 0) at the DI-input is used to select one of the two Input Registers. All bits are first shifted into an input shift register. After the rising edge of CSN the contents of the input shift register will be written to the selected Input Data Register only if a frame of exact 24 data bits are detected. Depending on bit 0 the contents of the selected status register will be transferred to DO during the current communication frame. Bit 1-17 controls the behavior of the corresponding driver. If bit 23 is zero, the device will go into the standby-mode. The bits 18 and 19 are used to control the current monitor multiplexer. Bit 22 is used to reset all status bits in both status registers. The bits in the status registers will be cleared after the current communication frame (rising edge of CSN).
4.7
Status register
This devices uses two status registers to store and to monitor the state of the device. No error bit (bit 0) is used as a fault bit and is a logical-NOR combination of bits 1-22 in both status registers. The state of this bit can be polled by the microcontroller without the need of a full SPI-communication cycle. If one of the over-current bits is set, the corresponding driver will be disabled. If the over-current recovery bit of the output is not set the microcontroller has to clear the over-current bit to enable the driver. If the thermal shutdown bit is set, all drivers will go into a high impedance state. Again the microcontroller has to clear the bit to enable the drivers.
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L9954 / L9954XP
Functional description of the SPI
4.8
SPI - Input data and status registers
Table 18.
Bit Name Comment Name Comment
SPI - input data and status registers 0
Input register 0 (write) Status register 0 (read)
23
Enable bit
If Enable Bit is set the device switches in active mode. If Enable Bit is cleared the device goes into standby mode and all bits are cleared. After power-on reset device starts in standby mode. If Reset Bit is set both status registers will be cleared after rising edge of CSN input.
Always 1
A broken VCC-or SPIconnection of the L9954 can be detected by the microcontroller, because all 24 bits low or high is not a valid frame.
22
21
In case of an overvoltage or undervoltage event the corresponding bit is set and the outputs are deactivated. If OC recovery This bit defines in VS voltage recovers to normal duty cycle combination with the overoperating conditions outputs current recovery bit (Input VS undervoltage are reactivated automatically Register 1) the duty cycle (if Bit 20 of status register 0 is 0: 12% 1: 25% in over-current condition of not set). an activated driver. Reset bit VS overvoltage Overvoltage/ Undervoltage recovery disable If this bit is set the microcontroller has to clear the status register after undervoltage / overvoltage event to enable the outputs. Depending on combination of bit 18 and 19 the current image (1/10.000) of the selected HS-output will be multiplexed to the CM output: Current monitor select bits Bit 19 0 1 Bit 18 0 0 1 1 Output OUT6 OUT1 OUT4 OUT5 Not ready bit In case of a thermal shutdown all outputs are switched off. The microcontroller has to clear the TSD bit by setting the Reset Bit to reactivate the outputs. The TW bit can be used for thermal management by the microcontroller to avoid a thermal shutdown. The microcontroller has to clear the TW bit. After switching the device from standby mode to active mode an internal timer is started to allow chargepump to settle before the outputs can be activated. This bit is cleared automatically after start up time has finished. Since this bit is controlled by internal clock it can be used for synchronizing testing events (e.g. measuring filter times).
20
Thermal shutdown
19
Temperature warning
18
0 1
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Functional description of the SPI Table 18.
Bit Name Comment Name
L9954 / L9954XP
SPI - input data and status registers 0 (continued)
Input register 0 (write) Status register 0 (read) Comment
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
OUT6 - HS on/off x (don't care) OUT5 - HS on/off OUT4 - HS on/off x (don't care) x (don't care) x (don't care) x (don't care) x (don't care) x (don't care) x (don't care) OUT3 - HS on/off OUT3 - LS on/off OUT2 - HS on/off OUT2 - LS on/off OUT1 - HS on/off OUT1 - LS on/off 0
OUT6 - HS over-current 0 OUT5 - HS over-current OUT4 - HS over-current 0 0 0 0 0 0 0 OUT3 - HS over-current OUT3 - LS over-current OUT2 - HS over-current OUT2 - LS over-current OUT1 - HS over-current OUT1 - LS over-current No error bit A logical NOR-combination of all bits 1 to 22 in both status registers. In case of an over-current event the corresponding status bit is set and the output driver is disabled. If the over-current Recovery Enable bit is set (Input Register 1) the output will be automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle (Bit 21). If the over-current recovery bit is not set the microcontroller has to clear the over-current bit (Reset Bit) to reactivate the output driver.
If a bit is set the selected output driver is switched on. If the corresponding PWM enable bit is set (Input Register 1) the driver is only activated if PWM1 (PWM2) input signal is high. The outputs of OUT1-OUT3 are half bridges. If the bits of HSand LS-driver of the same half bridge are set, the internal logic prevents that both drivers of this output stage can be switched on simultaneously in order to avoid a high internal current from VS to GND.
0
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L9954 / L9954XP Table 19.
Bit
Functional description of the SPI SPI - input data and status registers 1
Input register 1 (write) Name Comment Status register 1 (read) Name Comment
23
Enable bit
If Enable bit is set the device will be switched in active mode. If Enable Bit is cleared device goes into standby mode and all bits are cleared. After poweron reset device starts in standby mode.
Always 1
A broken VCC-or SPIconnection of the L9954 can be detected by the microcontroller, because all 24 bits low or high is not a valid frame. In case of an overvoltage or undervoltage event the corresponding bit is set and the outputs are deactivated. If Vs voltage recovers to normal operating conditions outputs are reactivated automatically.
22
OUT6 OC Recovery Enable
VS overvoltage
21
x (don't care)
VS undervoltage
20
OUT5 OC Recovery Enable
19
OUT4 OC Recovery Enable
In case of an over-current event the over-current status bit (Status Register 0) is set and the output is switched off. If the over-current Recovery Enable bit is set the output will be automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle (Bit 21 of Input Data Register 0). Depending on occurrence of Overcurrent Event and internal clock phase it is possible that one recovery cycle is executed even if this bit is set to zero.
In case of a thermal shutdown all outputs are switched off. The Thermal shutdown microcontroller has to clear the TSD bit by setting the Reset Bit to reactivate the outputs. The TW bit can be used for thermal management by the microcontroller to avoid a thermal shutdown. The microcontroller has to clear the TW bit. After switching the device from standby mode to active mode an internal timer is started to allow chargepump to settle before the outputs can be activated. This bit is only present during start up time. Since this bit is controlled by internal clock it can be used for synchronizing testing events(e.g. measuring filter times).
Temperature warning
18
x (don't care)
Not ready bit
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Functional description of the SPI Table 19.
Bit
L9954 / L9954XP
SPI - input data and status registers 1 (continued)
Input register 1 (write) Status register 1 (read) Name Comment Comment
Name
17 16 15
x (don't care) x (don't care) x (don't care) OUT3 OC Recovery Enable OUT2 OC Recovery Enable OUT1 OC Recovery Enable OUT6 PWM1 Enable x (don't care) OUT5 PWM2 Enable OUT4 PWM1 Enable x (don't care) x (don't care) x (don't care) x (don't care) OUT3 PWM1 Enable OUT2 PWM1 Enable OUT1 PWM1 Enable If the PWM1/2 Enable Bit is set and the output is enabled (Input Register 0) the output is switched on if PWM1/2 input is high and switched off if PWM1/2 input is low. OUT5 is controlled by PWM2 input. All other outputs are controlled by PWM1 input. After 50ms the bit can be cleared. If over-current condition still exists, a wrong load can be assumed.
OUT6 - HS open load 0 OUT5 - HS open load OUT4 - HS open load 0 The open load detection monitors the load current in each activated output stage. If the load current is below the open load detection threshold for at least 1 ms (tdOL) the corresponding open load bit is set. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3ms) can be used to test the open load status without changing the mechanical/electrical state of the loads.
14
13
12
0
11 10 9 8 7 6 5 4 3 2 1
0 0 0 0 0 OUT3 - HS open load OUT3 - LS open load OUT2 -HS open load OUT2- LS open load OUT1 - HS open load OUT1 - LS open load
0
1
No Error bit
A logical NORcombination of all bits 1 to 22 in both status registers.
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Packages thermal data
5
Packages thermal data
Figure 10. Packages thermal data
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Package and packing information
L9954 / L9954XP
6
6.1
Package and packing information
ECOPACK(R) packages
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark.
6.2
PowerSO-36TM package information
Figure 11. PowerSO-36TM package dimensions
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L9954 / L9954XP Table 20. PowerSO-36TM mechanical data
Package and packing information
Millimeters Symbol Min. Typ. Max.
A a1 a2 a3 b c D* D1 E E1 * E2 E3 e e3 G H h L M N R s 0.8 0 15.50 5.80 0.65 11.05 0 0.22 0.23 15.80 9.40 13.90 10.90 0.10
3.60 0.30 3.30 0.10 0.38 0.32 16.00 9.80 14.5 11.10 2.90 6.20
0.10 15.90 1.10 1.10
10 deg
8 deg
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Package and packing information
L9954 / L9954XP
6.3
PowerSSO-36TM package information
Figure 12. PowerSSO-36TM package dimensions
Table 21.
PowerSSO-36TM mechanical data
Millimeters Min. Typ. Max.
Symbol
A A2 a1 b c D* E* e e3 F G G1 H h k L N
2.15 0 0.18 0.23 10.10 7.4 10.1 0 0.55 -
0.5 8.5 2.3 -
2.45 2.35 0.1 0.36 0.32 10.50 7.6 0.1 0.06 10.5 0.4 8 0.85 10 deg
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L9954 / L9954XP Table 21.
Package and packing information PowerSSO-36TM mechanical data (continued)
Millimeters Min. Typ. Max.
Symbol
X Y
4.3 6.9
-
5.2 7.5
6.4
PowerSO-36TM packing information
Figure 13. PowerSO-36TM tube shipment (no suffix)
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Package and packing information Figure 14. PowerSO-36TM tape and reel shipment (suffix "TR")
L9954 / L9954XP
TAPE DIMENSIONS A0 B0 K0 K1 F P1 W 15.20 0.1 16.60 0.1 3.90 0.1 3.50 0.1 11.50 0.1 24.00 0.1 24.00 0.3
REEL DIMENSIONS
Base Qty Bulk Qty A (max) B (min) C (0.2) D (min) G (+2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4
All dimensions are in mm.
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Package and packing information
6.5
PowerSSO-36TM packing information
Figure 15. PowerSSO-36TM tube shipment (no suffix)
Base Qty Bulk Qty Tube length (0.5) A B C (0.1) All dimensions are in mm.
A
C
B
49 1225 532 3.5 13.8 0.6
Figure 16. PowerSSO-36TM tape and reel shipment (suffix "TR")
Reel dimensions
Base Qty Bulk Qty A (max) B (min) C (0.2) F G (+2 / -0) N (min) T (max) Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing All dimensions are in mm. W P0 (0.1) P D (0.05) D1 (min) F (0.1) K (max) P1 (0.1) 24 4 12 1.55 1.5 11.5 2.85 2
1000 1000 330 1.5 13 20.2 24.4 100 30.4
End
Start Top cover tape No components Components 500mm min No components
500mm min Empty components pockets sealed with cover tape. User direction of feed
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Revision history
L9954 / L9954XP
7
Revision history
Table 22.
Date
Document revision history
Revision Description of changes
23-Jan-2008
1
Initial release.
Table 21: PowerSSO-36TM mechanical data: - Deleted A (min) value - Changed A (max) value from 2.47 to 2.45 - Changed A2 (max) value from 2.40 to 2.35 - Changed a1 (max) value from 0.075 to 0.1 - Added F and k rows Table 21: PowerSSO-36TM mechanical data: - Changed X: minimum value from 4.1 to 4.3 and maximum value from 4.7 to 5.2 - Changed Y: minimum value from 6.5 to 6.9 and maximum value from 7.1 to 7.5
24-Jun-2009
2
17-May-2010
3
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Doc ID 14279 Rev 3
L9954 / L9954XP
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